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Publications of Tanguy Risset
Thesis
  1. T. Risset. Contribution à la compilation de nids de boucles sur silicium. Thèse d'habilitation à diriger des recherches, Université de Rennes 1, October 2000. [WWW]


  2. T. Risset. Parallélisation automatique: du modèle systolique à la compilation de nids de boucles. Thèse de doctorat, ENS-Lyon, February 1994.


Articles in journal or book chapters
  1. Mickaël Dardaillon, Kevin Marquet, Tanguy Risset, Jérôme Martin, and Henri-Pierre Charles. A New Compilation Flow for Software-Defined Radio Applications on Heterogeneous MPSoCs. ACM Transactions on Architecture and Code Optimization, 13, 2016. [WWW] [PDF]


  2. Mathieu Vallerian, Florin Doru Hutu, Guillaume Villemaud, Benoit Miscopein, and Tanguy Risset. A parallel unbalanced digitization architecture to reduce the dynamic range of multiple signals. Radio Science, April 2016. [WWW] [PDF]


  3. Mickaël Dardaillon, Kevin Marquet, Tanguy Risset, Jérôme Martin, and Henri-Pierre Charles. Cognitive Radio Programming Survey. In Naima Kaabouch and Wen-Chen Hu, editors, Handbook of Research on Software-Defined and Cognitive Radio Technologies for Dynamic Spectrum Management. IGI Global, October 2014. [WWW]


  4. Florin Doru Hutu, Bruno Allard, Fabrice Jumel, Mathieu Maranzana, Kevin Marquet, Lionel Morel, Luong Viet Phung, Tanguy Risset, Dominique Tournier, Guillaume Salagnac, and Jacques VERDIER. Formation par projet et opportunité d'accès à distance à des ressources pédagogiques. J3eA - Journal sur l'enseignement des sciences et technologies de l'information et des systèmes, 13(5):1-10, May 2014. [WWW] [PDF]


  5. Matthieu Gautier, Guillaume Villemaud, Cédric Lévy-Bencheton, Dominique Noguet, and Tanguy Risset. Digital Front-End in Wireless Communication and Broadcasting, chapter Cross-layer design and digital front-end for cognitive wireless link. Cambridge University Press, 2011.


  6. Tanguy Risset. Encyclopedia of Parallel Computing, chapter System on Chip, pages 412-413. Springer, 2011. [WWW]


  7. Tanguy Risset, Riadh Ben Abdallah, Antoine Fraboulet, and Jérôme Martin. Digital Front-End in Wireless Communication and Broadcasting, chapter Programming Models and Implementation Platforms for Software Defined Radio Configuration. Cambridge University Press, 2011. [WWW]


  8. Steven Derrien, Sanjay Rajopadhye, Patrice Quinton, and Tanguy Risset. High-Level Synthesis : From Algorithm to Digital Circuit, chapter 12: High-Level Synthesis of Loops Using the Polyhedral Model. Spinger, 2008. [WWW]


  9. Antoine Scherrer, Antoine Fraboulet, and Tanguy Risset. Networks-on-Chips: Theory and Practice, chapter 4: On-chip Processor Traffic Modeling for NoC Design. CRC Press, 2008. [WWW]


  10. C. Tayou Djameni, Patrice Quinton, Sanjay Rajopadhye, Tanguy Risset, and Maurice Tchuente. A reindexing based approach towards mapping of DAG with affine schedules onto parallel embedded systems. Journal of Parallel and Distributed Computing, 2008. Note: To Appear. [WWW]


  11. A. C. Guillou, P. Quinton, and T Risset. Hardware Synthesis for Systems of Recurrence Equations with Multi-Dimensionnal Schedule. International Journal of Embedded Systems (IJES), 3(4):271-284, 2008. [WWW]


  12. Antoine Scherrer, Antoine Fraboulet, and Tanguy Risset. Long-Range Dependence and On-chip Processor Traffic. Microprocessors and Microsystems, 2008. [WWW]


  13. Antoine Fraboulet and Tanguy Risset. Master Interface for On-Chip Hardware Accelerator Burst Communications. Journal of VLSI Signal Processing, 59:73-85, 2007. [WWW]


  14. S. Derrien, A. C. Guillou, P. Quinton, T. Risset, and C. Wagner. Domain-Specific Embedded Multiprocessors, chapter 7: Automatic Synthesis of Efficient Interfaces for Compiled Regular Architectures, pages 127-150. Marcel Dekker, 2003. [WWW]


  15. F. de Dinechin, T. Risset, M Manjunathaiah, and M Spivey. System Specification and Design Languages (best of FDL'02), chapter Design of highly parallel architectures with Alpha and Handel, pages 293-304. Kluwer, 2003. [WWW]


  16. S. Rajopadhye, T. Risset, and T. Tadonki. Le chemin algébrique sur réseaux linéaires. Technique et Science Informatique, 20(5):655-676, 2001. [WWW]


  17. E. Mémin and T. Risset. On the Study of VLSI Derivation for Optical Flow Estimation. International Journal of pattern recognition and Artificial Intelligence (IJPRAI), 14(4):441-462, June 2000. [WWW]


  18. E. Mémin and T. Risset. VLSI Design Methodology for Edge-Preserving Image Reconstruction. Real-Time Imaging, Special issue on Fast Energy Minimization-Based Imaging and Vision Techniques, 2000. [WWW]


  19. C. Tayou Djamegni, P. Quinton, S. Rajopadhye, and T. Risset. Derivation of Systolic Algorithms for the Algebraic Path Problem by Recurrence Transformations. Parallel Computing, 26:1429-1445, 2000. [WWW]


  20. T. Gautier, P. Le Guernic, P. Quinton, S. Rajopadhye, T. Risset, and I. Smarandache. Le projet Cairn : vers la conception d'architectures à partir de Signal et Alpha. In Collection Technique et scientifique des Télécommunications. CNET, 1997.


  21. P. Quinton, S. V. Rajopadhye, and T. Risset. On Manipulating Z-polyhedra using a Canonical Representation. Parallel Processing Letters, 7(2):181-194, June 1997. [WWW]


  22. M. Dion, T. Risset, and Y. Robert. Ressource-Constrained Scheduling of Partitioned Algorithms on Processor Arrays. Integration the VLSI journal, 20:139-159, 1994. [WWW]


  23. A. Darte, T. Risset, and Y. Robert. Application-Driven Architecture synthesis, chapter 3: Formal Methods for Solving the Algrebraic Path Problem. Kluwer Academic Publishers, 1993.


  24. P. Boulet, A. Darte, T. Risset, and Y. Robert. (Pen)-Ultimate Tiling?. Integration, the VLSI journal, 17, 1993. [WWW]


  25. J.F. Collard, P. Feautrier, and T. Risset. Construction of DO Loops from Systems of Affine Constraints. Parallel Processing Letters, 5:421-436, 1993. [WWW]


  26. T. Risset and Y. Robert. Synthesis of Processor Arrays for the Algebraic Path Problem: Unifying Old Results and Deriving New Architectures. Parallel Processing Letters, 1:19-28, 1991.


  27. T. Risset. Implementing Gaussian Elimination on a Matrix-Matrix Multiplication Systolic Array. Parallel Computing, 16:351-359, 1990.


Conference articles
  1. Wei Du, Jean-Marie Gorce, Tanguy Risset, Matthieu Lauzier, and Antoine Fraboulet. Compressive Data Aggregation on Mobile Wireless Sensor Networks for Sensing in Bike Races. In European Signal Processing Conference (EUSIPCO 2016), Budapest, Hungary, August 2016. European Association for Signal Processing (EURASIP). [WWW] [PDF]


  2. Florin Hutu, Guillaume Salagnac, Kevin Marquet, and Tanguy Risset. Plateforme de mesure de la consommation énergétique dédiée aux objets communicants. In Journées Scientifiques de l'URSI : Energie et Radiosciences, Rennes, France, March 2016. [WWW]


  3. Bertrand Massot, Tanguy Risset, Gregory Michelet, and Eric McAdams. Mixed Hardware and Software Embedded Signal Processing Methods for in-situ Analysis of Cardiac Activity. In 9th International Joint Conference on Biomedical Engineering Systems and Technologies - : Smart-BIODEV,, volume 4, Rome, Italy, 2016. [WWW] [PDF]


  4. Bertrand Massot, Tanguy Risset, Gregory Michelet, and Eric McAdams. A wireless, low-power, smart sensor of cardiac activity for clinical remote monitoring. In 2015 17th International Conference on E-health Networking, Application and Services (HealthCom) (IEEE Healthcom 2015, Boston, United States, pages 487-493, November 2015. IEEE. [WWW] [PDF]


  5. Mathieu Vallerian, Guillaume Villemaud, Florin Hutu, Benoit Miscopein, and Tanguy Risset. A parallel unbalanced digitization architecture to reduce the dynamic range of multiple signals. In 1st URSI Atlantic Radio Science Conference (URSI AT-RASC), 2015, Radio Science Conference (URSI AT-RASC), 2015 1st URSI Atlantic Proceedings, Gran Canaria, Spain, May 2015. Note: Best student paper finalist. [WWW]


  6. Mathieu Vallérian, Florin Hutu, Benoît Miscopein, Guillaume Villemaud, and Tanguy Risset. Additive companding implementation to reduce ADC constraints for multiple signals digitization. In IEEE International Conference on New Circuits and Systems Conference (NEWCAS), Grenoble, France, June 2015. [WWW] [PDF]


  7. Mickaël Dardaillon, Kevin Marquet, Tanguy Risset, Jérôme Martin, and Henri-Pierre Charles. A Compilation Flow for Parametric Dataflow: Programming Model, Scheduling, and Application to Heterogeneous MPSoC. In International Conference on Compilers, Architecture and Synthesis for Embedded Systems (CASES), New Delhi, India, October 2014. [WWW] [PDF]


  8. Mickaël Dardaillon, Kevin Marquet, Tanguy Risset, Jerome Martin, and Henri-Pierre Charles. Compilation for heterogeneous SoCs : bridging the gap between software and target-specific mechanisms. In workshop on High Performance Energy Efficient Embedded Systems - HIPEAC, Vienne, Autriche, January 2014. [WWW] [PDF]


  9. Mickaël Dardaillon, Kevin Marquet, Tanguy Risset, Jérôme Martin, and Henri-Pierre Charles. Contrôle d'application flot de données pour les systèmes sur puces : étude de cas sur la plateforme Magali. In Pascal Felber, Laurent Philippe, Etienne Riviere, and Arnaud Tisserand, editors, ComPAS, Neuchâtel, Suisse, pages 1 - 12, April 2014. [PDF]


  10. Matthieu Lauzier, Antoine Fraboulet, Jean-Marie Gorce, and Tanguy Risset. Distributed Mobile Group Detection Algorithms: Application to Cycling Race. In Ninth IEEE Workshop on Practical Issues in Building Sensor Network Applications 2014, Edmonton, Canada, September 2014. [WWW] [PDF]


  11. Matthieu Lauzier, Antoine Fraboulet, Jean-Marie Gorce, and Tanguy Risset. Live Group Detection for Mobile Wireless Sensor Networks. In Ninth International Conference on Body Area Networks, London, Great Britain, September 2014. [PDF]


  12. Albdelbassat Massouri and Tanguy Risset. FPGA-based Implementation of Multiple PHY Layers of IEEE 802.15.4 Targeting SDR Platform. In SDR-WInnComm, Schaumburg, Illinois, États-Unis, 2014. Wireless Innovation Forum. [WWW] [PDF]


  13. Mathieu Vallerian, Guillaume Villemaud, Benoit Miscopein, Tanguy Risset, and Florin Hutu. SDR for SRD: ADC specifications for reconfigurable gateways in urban sensor networks. In IEEE Radio Wireless Symposium, Newport Beach, États-Unis, January 2014. [WWW] [PDF]


  14. Guillaume Villemaud, Zhaowu Zhan, Florin Hutu, Tanguy Risset, and Jean-Marie Gorce. Study of a Full-Duplex Dual- Band OFDM Transceiver. In DUPLO Workshop on Full - Duplex Radios and Systems, Oulu, Finland, June 2014. [WWW]


  15. Mickaël Dardaillon, Cédric Lauradoux, and Tanguy Risset. Hardware Implementation of the GPS authentication. In ReConFig - International Conference on ReConFigurable Computing and FPGAs, Cancun, Mexico, December 2012. [WWW]


  16. Mickaël Dardaillon, Kévin Marquet, Tanguy Risset, and Antoine Scherrer. Software Defined Radio Architecture Survey for Cognitive Testbeds. In Wireless Communications and Mobile Computing Conference (IWCMC), 2012 8th International, Limassol, Cyprus, September 2012. [WWW] [PDF]


  17. Guillaume Villemaud, Cédric Lévy-Bencheton, and Tanguy Risset. Performance Evaluation of Multi-antenna and Multi-mode Relays Using a Network Simulator. In EUCAP 2012, Prague, Czech Republic, March 2012. [WWW]


  18. Cédric Lévy-Bencheton, Doreid Ammar, and Guillaume Villemaud, and Tanguy Risset. Multi-mode relay simulations: an energy evaluation on WSNet. In Proceedings of the IEEE Radio and Wireless Symposium (RWS) 2011, Phoenix, AZ, USA, January 2011.


  19. C. Lévy-Bencheton, G. Villemaud, and T. Risset. Toward an energy reduction in mobile relays: combining MIMO and multi-mode. In IFIP Wireless Days, Niagara Falls, Canada, October 2011. [WWW]


  20. Riadh Ben Abdallah, Tanguy Risset, Antoine Fraboulet, and Jerome Martin. Virtual Machine for Software Defined Radio: Evaluating the Software VM Approach. In International Conference on Embedded software and systems (ICESS), Bradford, UK, pages 1970-1977, 2010. IEEE Computer Society. [WWW]


  21. Riadh Ben Abdallah, Tanguy Risset, Antoine Fraboulet, and Yves Durand. The Radio Virtual Machine: A solution for SDR portability and platform reconfigurability. In Reconfigurable Architectures Workshop (RAW), Anchorage, USA, pages 1-4, 2009. IEEE Computer Society. [WWW]


  22. Alexandru Plesco and Tanguy Risset. Coupling Loop Transformations and High-Level Synthesis. In Symposium en Architecture de machines (Sympa 2008), Fribourg 2008, 2008. ACM Press. [WWW]


  23. Antoine Scherrer, Antoine Fraboulet, and Tanguy Risset. Long-Range Dependence and On-chip Processor Traffic. In ReCoSoc: Reconfigurable Communication-centric SoCs, Montpellier, France, June 2007. [WWW]


  24. Antoine Fraboulet, Antoine Scherrer, and Tanguy Risset. Automatic Phase detection for Stochastic On-Chip Traffic Generation. In , seoul, South Corea, pages 88 - 93, October 2006. ACM Press. [WWW]


  25. Antoine Scherrer, Antoine Fraboulet, and Tanguy Risset. A Generic Multi-Phase On-Chip Traffic Generation Environment. In IEEE 17th International Conference on Application-Specific Systems, Architectures and Processors (ASAP'06), Steamboat Springs, Colorado, USA, September 2006. [WWW]


  26. C. Tayou Djamegni, P. Quinton, S. Rajopadhye, T. Risset, and Tchuente M.. Une approche itérative pour l'allocation des tâches sur réseaux réguliers. In M. Tchuente, editor, 8ème Colloque Africain sur la Recherche Informatique, Cotonou, Bénin, 2006. [WWW]


  27. Alain Darte, Steven Derrien, and Tanguy Risset. Hardware/Software Interface for Multi-Dimensional Processor Arrays. In IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP), pages 28-35, 2005. IEEE Computer Society Press. [WWW]


  28. Antoine Fraboulet and Tanguy Risset. Efficient On-Chip Communications for Data-Flow IPs. In Application Specific Array Processors (ASAP'04), pages 293-303, 2004. IEEE Computer Society Press. [WWW]


  29. Antoine Fraboulet, Tanguy Risset, and Antoine Scherrer. Cycle Accurate Simulation Model Generation for SoC Prototyping. In SAMOS, pages 453-462, 2004.


  30. Antoine Scherrer, Antoine Fraboulet, and Tanguy Risset. Cycle Accurate Simulation Model Generation for SoC Prototyping. In Andy D. Pimentel and Stamatis Vassiliadis, editors, Computer Systems: Architecture, Modeling, and Simulation (SAMOS 2004), volume 3133 of LNCS, pages 453-462, July 2004. Springer Verlag. [WWW]


  31. Antoine Scherrer, Tanguy Risset, and Antoine Fraboulet. Hardware Wrapper Classification and Requirements for On-Chip Interconnects. In Signaux, Circuits et Systèmes 2004, Monastir, Tunisie, pages 31-34, March 2004. [WWW]


  32. A. C. Guillou, P. Quinton, and T Risset. Hardware Synthesis for Multi-Dimensionnal Time. In IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP 2003), The Hague, The Netherlands, June 2003. [WWW]


  33. D. Cachera and T. Risset. Advances in Bit Width Selection Methodology. In IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP 2002), San Jose, California, July 2002. [WWW]


  34. F. Dupont de Dinechin, M. Manjunathaiah, T. Risset, and M. Spivey. Design of Highly Parallel Architectures with Alpha and Handel. In Forum on Specification & Design Langages (FDL 2002), Marseille, September 2002. [WWW]


  35. D. Cachera, P. Quinton, S. Rajopadhye, and T. Risset. Proving Properties of Multidimensional Recurrences with Application to Regular Parallel Algorithms. In 6th International Workshop on Formal Methods for Parallel Programming: Theory and Applications (FMPPTA), San Francisco, April 2001. [WWW]


  36. A.-C. Guillou, F. Quilleré, P. Quinton, S. Rajopadhye, and T. Risset. Hardware Design Methodology with the Alpha Language. In FDL'01, Lyon, France, September 2001. [WWW]


  37. M Manjunathaiah, G. M. Megson, T. Risset, and S. Rajopadhye. Uniformization of Affine Dependence Programs for Parallel Embedded System Design. In L.M. Ni and M. Valero, editors, Internationnal Conference on Parallel Processing, Valencia, Spain, pages 205-213, 2001. [WWW]


  38. P. Quinton and T. Risset. Structured Scheduling of Recurrence Equations: Theory and Practice. In Proc. of the System Architecture MOdelling and Simulation Workshop, Lecture Notes in Computer Science, 2268, Samos, Greece, pages 112-134, 2001. Springer Verlag. [WWW]


  39. S. Derrien and T. Risset. Interfacing compiled FPGA programs: the MMAlpha approach. In A. Arabnia, editor, PDPTA2000: Second International Workshop on Engineering of Reconfigurable Hardware/Software Objects, June 2000. CSREA Press. [WWW]


  40. A.C. Guillou, P. Quinton, and T. Risset. Automatic Design of VLSI Pipelined LMS Architectures. In 2000 IEEE Canadian Conference on Electrical & Computer Engineering, Trois Rivières, Canada, August 2000. [WWW]


  41. A. Mozipo, D. Massicote, P. Quinton, and T. Risset. A Parallel Architecture for Adaptative Channel Equalization Based On Kalman Filter Using MMAlpha. In 1999 IEEE Canadian Conference on Electrical & Computer Engineering, 1999.


  42. E. Mémin and T. Risset. Full Alternate Jacobi Minimization and VLSI Derivation of Hardware for Motion Estimation. In Int. Workshop on Parallel Image Processing and Analysis, IWPIPA'99, Madras, India, January 1999. [WWW]


  43. S. Rajopadhye, T. Risset, and C. Tadonki. The Algebraic Path Problem Revisited. In Fifth International Euro-Par Conference, Toulouse, France, pages 698-707, August 1999. [WWW]


  44. T. Risset and Y. Saouter. Synthèse de haut niveau d'un co-processeur pour le calcul des bases de Grobner. In 5eme Symposium en architecture nouvelles de machines (Sympa'5), Rennes, June 1999. [WWW]


  45. S. Balev, P. Quinton, S. V. Rajopadhye, and T. Risset. Linear Programming Models for Scheduling Systems of Affine Recurrence Equations -- a Comparative Study --. In 10th ACM Symposium on Parallel Algorithms and Architectures (SPAA), 1998. [WWW]


  46. A. Mozipo, D. Massicotte, P. Quinton, and T. Risset. Automatic Synthesis of a Parallel Architecture for Kalman Filtering using MMAlpha. In International Conference on Parallel Computing in Electrical Engineering (PARELEC 98), Bialystok, Poland, pages 201-206, September 1998. [WWW]


  47. C. Tayou Djamegni, P. Quinton, S. Rajopadhye, and T. Risset. Derivation Of Systolic Algorithms For The Algebraic Path Problem By Recurrence Transformations. In M. Tchuente, editor, 4ème Colloque Africain sur la Recherche Informatique, Dakar, Sénégal, pages 551,564, October 1998. Presse Universitaire de Dakar.


  48. F. Dupont de Dinechin, T. Risset, and S. Robert. Hierarchical Static Analysis for Improving the Complexity of Linear Algebra Algorithms. In Internationnal Conference on Parallel Computing (PARCO), 1997. North Holland. [WWW]


  49. P. Le Moenner, L. Perraudeau, S. Rajopadhye, T. Risset, and P. Quinton. Generating Regular Arithmetic Circuits with AlpHard. In Massively Parallel Computing Systems (MPCS'96), May 1996. [WWW]


  50. P. Quinton, S. V. Rajopadhye, and T. Risset. Extension of the Alpha Language to Recurrences on Sparse Periodic Domains. In J. Fortes et al., editor, Int. Conf. on Application Specific Array Processors, Chicago, Illinois, pages 391-401, 1996. IEEE Computer Society Press. [WWW]


  51. P.Y. Calland and T. Risset. Precise Tiling for Uniform Loop Nests. In C. Mongenet et al., editor, Application Specific Array Processors, pages 330-337, 1995. IEEE Computer Society Press. [WWW]


  52. M. Dion, T. Risset, and Y. Robert. Resource-constrained scheduling of partitioned algorithms on processor arrays. In EuroMicro Workshop on Parallel and Distributed Processing, pages 571-580, 1995. IEEE Computer Society Press.


  53. F Dupont De Dinechin, P. Quinton, and T. Risset. Structuration of the Alpha Language. In W.K. Giloi, S. Jahnichen, and B.D. Shriver, editors, Massively Parallel Programming Models, pages 18-24, 1995. IEEE Computer Society Press. [WWW]


  54. P Boulet, A. Darte, T. Risset, and Y. Robert. (Pen)-Ultimate Tiling. In Scalable High-Performance Computing Conference, 1994. [WWW]


  55. T. Risset. Applying Semi-Systolic Techniques to SIMD Programming. In C. Girault, editor, Applications in Parallel and Distributed Computing (IFIP Transactions), pages 103-112, 1994. North-Holland. [WWW]


  56. A. Darte, T. Risset, and Y. Robert. Loop Nest Scheduling and Transformations. In J.J Dongarra et al., editor, Environments and tools for parallel scientific computing, pages 309-332, 1993. North-Holland.


  57. T. Risset and S. Song. A Real Time Systolic Algorithm for On-the-fly Hidden Surface Removal. In L. Dadda and B. Wah., editors, Application Specific Array Processors, pages 238-249, 1993. IEEE Computer Society Press.


  58. T. Risset. A Method to Synthesize Modular Systolic Arrays With Local Broadcast Facility. In J. Fortes et al., editor, Application Specific Array Processors, pages 415-428, 1992. IEEE Computer Society Press.


  59. A. Darte, T. Risset, and Y Robert. Synthesizing Systolic Arrays: some Recent Developments. In M. Valero et al., editor, Application Specific Array Processors, pages 372-386, 1991. IEEE Computer Society Press.


  60. A. Darte, Y. Robert, and T. Risset. Systolic Systems. In P.J. Hargraven, editor, 2nd IEE Int. Specialist Seminar on Parallel Digital Processors, volume 334 of IEEE Conference Publication, pages 6-10, 1991. IEEE Press.


  61. T. Risset. Linear Systolic Arrays for Matrix Multiplication: Comparisons of Existing Methods and New Results. In Proc. 2nd Workshop on Algorithms and VLSI parallel architecture, 1991.


  62. T. Risset and Y. Robert. Uniform but Non-Local DAGs: a Trade-off between Pure Systolic and SIMD Solutions. In M. Valero et al., editor, Application Specific Array Processors, pages 296-308, 1991. IEEE Computer Society Press.


Internal reports
  1. Mathieu Vallérian, Florin Hutu, Guillaume Villemaud, Benoît Miscopein, and Tanguy Risset. A study of companding approaches to alleviate the ADC constraints when demodulating multiple signals. Research Report RR-8683, Inria - Research Centre Grenoble -- Rhône-Alpes ; INRIA, February 2015. [WWW]


  2. Antoine Scherrer, Antoine Fraboulet, and Tanguy Risset. Analysis and Synthesis of Cycle-Accurate On-Chip Traffic with Long-Range Dependence. Technical report 2005-53, LIP, ENS-Lyon, December 2005.


  3. D. Cachera, S. Rajopadhye, T. Risset, and C. Tadonki. Parallelization of the Algebraic Path Problem on Linear SIMD/SPMD Arrays. Technical report 1346, Irisa, 2000. [WWW]


  4. S.P.K. Nookala and T. Risset. A Library for Z-polyhedral Operations. Technical report 1330, Irisa, 2000. [WWW]


  5. F. Bardoult, P. Quinton, S. Rajopadhye, and T. Risset. Synthesis of data-flow interfaces for regular parallel programs. Technical report 1260, Irisa, September 1999. [WWW]


  6. F. Dupont de Dinechin, P. Quinton, S. Rajopadhye, and T. Risset. First Steps in Alpha. Technical report 1244, Irisa, 1999. [WWW]


  7. T. Risset, F. Dupont de Dinechin, and S. Robert. Structured Scheduling of Reccurence Equations. Technical report 1140, IRISA, 1997. [WWW]


  8. T. Risset and Y. Saouter. A Linear Systolic Array for the Computation of Gröbner Basis. Technical report 1069, Irisa, 1996. [WWW]


Miscellaneous
  1. Albdelbassat Massouri, Leonardo Cardoso, Benjamin Guillon, Florin Hutu, Guillaume Villemaud, Tanguy Risset, and Jean-Marie Gorce. CorteXlab: An Open FPGA-based Facility for Testing SDR & Cognitive Radio Networks in a Reproducible Environment. INFOCOM'2014 Demo/Poster Session, April 2014. [WWW]


  2. Riadh Ben Abdallah, Tanguy Risset, Antoine Fraboulet, and Jérôme Martin. Dispositif, chaine et procédé de traitement de données, et programme d'ordinateur correspondant. Patent CEA/Inria, ref: DD11158 ST, June 2011.


  3. Riadh Ben Abdallah, Tanguy Risset, Antoine Fraboulet, and Jérôme Martin. Implementing a Radio Virtual Machine on the MAGALI chip. Wireless Innovation Forum, June 2010.


  4. P. Quinton and T. Risset. Designing Parallel Programs and Integrated Circuits. 8th International Mathematica Symposium (IMS'06), June 2006.


  5. D. Cachera, S. Rajopadhye, T. Risset, and C. Tadonki. A Coarse Grain Algorithm for the Algebraic Path Problem and its Optimal Parallelization, 2005. Note: Submitted to Algorithmica Special Issue on Coarse Grained Parallel Algorithms.


  6. A. Scherrer, A. Fraboulet, and T. Risset. Hardware-Software Fast and Accurate Prototyping with Soclib & MMAlpha. University Booth Demonstration, February 2004. Note: University booth stand. [WWW]


  7. A.C. Guillou, P Quinton, T. Risset, C. Wagner, and D Massicotte. High Level Design of Digital Filters in Mobile Communications. DATE Design Contest 2001, March 2001. Note: Second place. [WWW]


  8. P. Quinton and T. Risset. MMAlpha: a toolbox for silicon compilation. University Booth Demonstration, March 2000. Note: University booth stand.



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Last modified: Fri Jan 20 11:27:25 2017
Author: trisset.


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